library verilog;
use verilog.vl_types.all;
entity uart_rx is
    generic(
        IDLE            : vl_logic_vector(0 to 3) := (Hi0, Hi0, Hi0, Hi1);
        START           : vl_logic_vector(0 to 3) := (Hi0, Hi0, Hi1, Hi0);
        DATA            : vl_logic_vector(0 to 3) := (Hi0, Hi1, Hi0, Hi0);
        STOP            : vl_logic_vector(0 to 3) := (Hi1, Hi0, Hi0, Hi0)
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        rx              : in     vl_logic;
        rx_done_flag    : out    vl_logic;
        data_out        : out    vl_logic_vector(7 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of IDLE : constant is 1;
    attribute mti_svvh_generic_type of START : constant is 1;
    attribute mti_svvh_generic_type of DATA : constant is 1;
    attribute mti_svvh_generic_type of STOP : constant is 1;
end uart_rx;
